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Embedded Designer — from schematic to Gerber
Schematic, ERC, 1–32 layer PCB, controlled impedance, autorouting, DRC, manufacturing outputs, thermal/power-integrity and real-time schedulability analysis; flashing to STM32 boards.
1–32 layersGerber RS-274X + ExcellonERC · DRCRTA · thermal · PI
Screens
Inside the panel
Schematic, placement, routing, check reports and manufacturing outputs.
Schematic
Catalog and netlist
- ✓6,550-part catalog — category, pin IDs, temperature-class tags (temp:-55/-40/0)
- ✓Netlist — place/delete parts, connect/disconnect pins, R/C/L/V/I values (10k, 100nF, 4k7…)
- ✓Hierarchical sheets — Power/MCU/Analog/IO/Sensor; automatic assignment
- ✓ERC — shorts, power↔signal/GND, bus-family mismatch, I2C address clash, isolation-barrier bridging, floating power/GND, stack-up; false-positive acknowledgement
- ✓MNA DC solution — I²R power loss in resistors (input to thermal analysis)
PCB
Stack-up, placement, routing
- ✓1–32 layers — symmetric stack-up with automatic inner GND/Power planes; board size
- ✓Controlled impedance — Z0/Zdiff target, εr, dielectric/copper thickness, fab-house DRC; IPC-2141 closed form verified with a 2D FDM field solver (~5–15%)
- ✓Placement — functional floorplan, edge-bound connectors/antenna, power↔sensitive separation, decap proximity, thermal/WCET co-optimisation; move/lock/rotate/side/face-outward
- ✓Routing — net classes, trace width/impedance/diff pairs/length matching (meander), via cost and effort, preferred layer, push-and-shove, per-net/per-region reroute, rip-up, net lock, guard, inner planes
- ✓DRC — annular ring, acid traps, trace-via, pad-trace, via-via clearances
Analysis and manufacturing
Reports and outputs
- ✓Gerber RS-274X + Excellon — F/B Cu, F/B Mask, F Paste, F SilkS, Edge Cuts, inner Cu; PTH/NPTH; manufacturing verification file
- ✓BOM and Pick&Place — CSV; single HTML manufacturing compliance report (ERC + DRC + RTA + thermal)
- ✓Electro-thermal — power loss → θja → steady-state temperature, over-temperature warnings, SVG heat map (first-order model)
- ✓Power integrity — missing decoupling, power budget, DC/IR drop
- ✓Real-time schedulability (RTA) — WCET/deadline, CPU utilisation, RM/EDF bounds, end-to-end chain latency
- ✓Boards and flashing — STM32F746G-DISCO, Nucleo-F746ZG, STM32F407 Discovery, bluepill; OpenOCD / STM32CubeProgrammer; ThreadX template; serial monitor
- ✓CAD bridge — bring the generated board into the 3D scene and auto-generate the enclosure with standoffs and connector cut-outs (Hardware bundle)
- ✓AI assistant — 47 full-authority tools; external command channel
Scope note: The thermal model is first-order (inter-component conduction is not fully modelled); there is no SPICE time-domain simulation or time-domain signal-integrity analysis; the 3D board view is via the CAD bridge.